This invention relates to a semiconductor device wherein a depletion or inversion layer induced in the surface portion of a semiconductor acts as the base of a transistor.
A transistor in which an inversion layer acts as a base was announced in Lecture No. 14P-A-3 at the 45th Science Lecture Meeting of the Applied Physics Society, Japan, Oct. 12, 1984. The structure of this earlier device is shown in FIG. 1 from which it will be noted that a first semiconductor region 1 is formed in its surface portion with an SiO.sub.2 insulation film 2 of a thickness permitting tunneling (20-60A) and a metallic electrode 3 is formed on the insulation film 2. Application of a bias to the metallic electrode 3 induces an inversion layer 4 which serves as the base.
In this conventional transistor, a base contact region 5 formed of a p-type semiconductor is provided as joined with the inversion layer 4 acting as the base and the potential of the inversion layer 4 is controlled by applying control voltage to the contact region 5, whereby the current flowing between the metallic electrode 3 and the first semiconductor region 1 can be controlled. More specifically, the device operates as a transistor in which the metallic electrode 3 acts as the emitter, the first semiconductor region 1, which is of n-type, as the collector and the inversion layer 4, which is in electrical contact with the p-type base contact region 5, as the base. Thus, the injection of carriers from the emitter into the base region relies on the Fowler-Nordheim tunnel effect in the SiO.sub.2 forming the insulation layer. That is to say, it makes use of the tunnel effect wherein the carriers are transported through the forbidden band. As a result, the operating current density becomes low. Therefore, while the device can be effectively applied for unit gates, cells and the like in LSIs, it is inappropriate for applications in which a load of large capacity has to be charged rapidly and thus has no potential for use in high-speed devices. Moreover, it is an unstable device in the sense that it is susceptible to operational fluctuations over time. A prior art heteroemitter bipolar transistor is disclosed in Japanese Patent Application Public Disclosure No. SHO 59-227161. Further, in the conventional hetero-emitter bipolar transistors a base region containing impurities at a high concentration is formed on the upper surface or in the surface portion of the first semiconductor region and an emitter containing impurities at a high concentration is then formed on the base region by hetero-epitaxial growth. However, in such an arrangement, since there is a limit on the temperature usable in the heat treatment carried out for preventing increase in base width, the productivity and operational efficiency are low. There is also the disadvantage that the process of epitaxially growing the emitter region on a base region having a high impurity concentration is apt to give rise to lattice defects, whereby the performance of the device is degraded and the production yield becomes low.